NASA spaceflight computer to use SiFive RISC-V processor cores • The Register

Chip designer SiFive said on Tuesday that its RISC-V compatible processor cores will power NASA’s recently announced high-performance spaceflight computer (HPSC).

The computer system will form the backbone of future manned and unmanned missions, including those to the Moon and Mars. Its microprocessor will be developed under a three-year, $50 million deal with SiFive and Microchip, the systems-on-chip designer and home of the PIC family of microcontrollers.

The HPSC processor replaces the aging PowerPC-based BAE RAD750, which was introduced more than two decades ago and has flown in countless spacecraft, including the Curiosity and Perseverance rovers and the James Web Space Telescope.

“The last chip used by NASA lasted decades,” said Jack Kang, business development manager at SiFive. The register. “This chip is going to be used for decades to come.”

SiFive says the 12-core processor it’s designing with Microchip will deliver a 100x performance improvement over its predecessor while delivering superior power efficiency through its ability to disable various sections of the chip when not in use. not used. This performance is important, Kang said, to enable a new generation of autonomous rovers, vision processing, spaceflight, guidance and communication applications beyond Earth’s atmosphere and orbit.

“A lot of these things are really well suited to vectors,” he said, referring to vector math.

Speaking of which, the HPSC processor will feature eight of SiFive’s AI/ML-optimized X280 vector processing cores in addition to four general-purpose RISC-V processor cores.

The X280 is a RISC-V processor core with advanced vector math extensions. As its name suggests, it extends the standard RISC-V instruction set architecture (ISA), which means it can execute application code as well as instructions to speed up vector processing by doing in hardware.

SiFive claims that these vector extensions allow the chip designer to achieve six times the performance of standard RISC-V vector instructions, while maintaining the platform’s low-power envelope.

However, beyond pure performance, chips destined for outer space have to deal with harsh operating conditions.

“If you look at these space-going chips and these environments, they have a lot going for them,” Kang said. “Part of that comes from the architecture; some comes from the design of the chip itself; some comes from the process.

Architecturally, he says, SiFive’s design benefits from the company’s chip development work for automotive applications. “Automotive has very similar type requirements for high reliability, fault tolerance and functional safety,” Kang said.

RISC-V has garnered considerable attention and hundreds of millions of dollars of investment in recent years, in part due to the open, free, and lightweight nature of its ISA. The core architecture, as a typical RISC design, has less than 50 instructions on which official and third-party extensions can be added to bring more instructions to a processor core, depending on its operating needs.

For example, if you don’t want floating point math speedup, you can stick with integer base and extensions. But if you want an FPU, atomic instruction support, and other features, you are free to implement these defined extensions into your CPU core.

NASA and Microchip’s decision to go with a RISC-V design had to do with more than the novelty of an open, royalty-free ISA. According to Kang, the RISC-V architecture is one of the most likely to have a large developer base in 10, 15 or even 20 years, and would therefore be a safe bet for NASA.

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“If you look at today’s PowerPC chips – we’ve been using them for decades – how many PowerPC programmers are there now,” he said.

While we now know the underlying CPU architecture of NASA’s HPSC processor, we have to wait and see how the design will eventually be implemented, such as radiation hardening that will be used as well as any other specialized processing required by the space fairing semiconductors.

This is probably one of the reasons why NASA turned to Microchip to develop the HPSC processor: Microchip announces several radiation-hardened chips. So SiFive provides the CPU IP address while Microchip lays out the cores on a space-survivable die with the necessary support circuitry – and bam, RISC-V in space.

“This state-of-the-art spaceflight processor will have a huge impact on our future space missions and even technologies here on Earth,” said Niki Werkheiser, director of technology maturation at NASA’s Space Technology Mission Directive, in a statement.

“This effort will amplify existing spacecraft capabilities and enable new ones and could ultimately be used by virtually all future space missions, all benefiting from more capable flight computing.” ®

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