Intel shows research to pack more computing power into chips beyond 2025


The Intel logo is displayed on computer screens at SIGGRAPH 2017 in Los Angeles, California, the United States, July 31, 2017. REUTERS / Mike Blake / File Photo

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Dec.11 (Reuters) – Research teams at Intel Corp (INTC.O) on Saturday unveiled work that the company says will help it speed up and scale down computer chips over the next decade, with several technologies to stack parts of chips on top of each other.

Intel’s Research Components Group presented the work in papers at an international conference to be held in San Francisco. The Silicon Valley company is striving to regain its lead in making the smallest, fastest chips it has lost in recent years to rivals such as Taiwan Semiconductor Manufacturing Co (2330.TW) and Samsung Electronics Co Ltd (005930.KS).

While Intel CEO Pat Gelsinger outlined business plans to recapture that lead by 2025, the research unveiled on Saturday provides a glimpse of how Intel plans to compete beyond 2025.

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One of the ways that Intel is putting more computing power into chips by stacking three-dimensional “tiles” or “chips” rather than creating two-dimensional one-piece chips. Intel showed work on Saturday that could allow 10 times more connections between stacked tiles, meaning more complex tiles can be stacked on top of each other.

But perhaps the biggest breakthrough shown on Saturday was a research paper demonstrating a way to stack transistors – tiny switches that form the most basic building blocks of chips by representing the 1s and 0s of digital logic. – on top of each other.

Intel believes the technology will cause a 30-50% increase in the number of transistors it can pack in a given area of ​​a chip. The increase in the number of transistors is the main reason that chips have consistently gotten faster over the past 50 years.

“By stacking devices directly on top of each other, we are clearly saving space,” Paul Fischer, director and senior senior engineer of Intel’s Components Research Group, told Reuters. “We are reducing interconnect lengths and actually saving energy, which makes it not only more cost effective, but also more efficient. “

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Reporting by Stephen Nellis in San Francisco Editing by Nick Zieminski

Our standards: Thomson Reuters Trust Principles.


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